PCL and PCLATH
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indiThe 16F84 has 1k of program memory (000–3FF), requiring a 10-bit address; the tprogram counter (PC) specifies the address of the instruction to fetch for execution;The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The 8-bit PCL (program counter low byte) can only select one of 256 addresses. The 1k of program memory is therefore divided into four 256 word blocks (pages), one of which is selected with 2 extra bits in the PCLATH (program counter latch high) register. this register contains the PC<12:8> bits and is not directly readable or writable. The PCL provides the address within each page of memory and is fully readable and writable. When a program jump is executed, PCL and PCLATH are modified automatically, that is, CALL and GOTO use a full 11-bit operand for jumps, so do not require any special manipulation of the address for jumping across page boundaries. However, if PCL is modified by a direct write under program control, PCLATH bits 0 and 1 may need to be manipulated to cross page boundaries successfully.In other PIC devices, there may be other limitations to program branching operations. For example, CALL instructions in the 12C5XX group are limited to the first 256 locations of the program, even though the overall memory may be up to 1k.rect addressing.
Memeory address wrapping
The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-03FFh) are physically implemented. Accessing a location above the physically implemented address will cause a wraparound. For example, for locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h, the instruction will be the same. The RESET vector is at 0000h and the interrupt vector is at 0004h.