Special function registers
The special function registers are memory registers which is used for special dedicated functions. These registers perform various dedicated functions inside the PIC chip. Each special function inside this PIC chip is controlled by using these registers. These registers are used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are normally implemented as in the form of static RAM memory. A list of these registers is given in the tables below. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
SFRs are the gateway to interaction between the CPU and the peripherals. To the CPU, an SFR acts more or less like a normal memory location—you can usually write to it or read from it. What makes it “special” is that the bits of that memory location have a dual purpose. Each bit is wired across to one or other of the microcontroller peripherals. Each is then used either to set up the operating mode of the peripheral or to transfer data between the peripheral and the microcontroller core.
The 16F84 Special File Registers set is organized in two banks, with the most commonly used registers in the default bank 0. Some of the control registers, such as the port data direction registers, TRISA and TRISB, and the OPTION register, are mapped into bank 1. Many of the SFRs can be accessed in either bank. Others have special access instructions, namely TRIS to write the Port A and B data direction registers, and OPTION which is used to set up the real time clock counter.
In another words, SFR is an area of data memory dedicated to registers that are required for configuration and dataflow control. This dedicated memory area is divided into a number of special function registers which can not be used as general purpose registers by the programmer. The special function registers are TMR0, OPTION, PCL, STATUS, FSR, PORTA, PORTB, TRISA, TRISB, EEDATA, EECON1, EEADR, EECON2, PCLATH and INTCON and are situated in the data memory locations shown in Figure below
Legend: x = unknown, u = unchanged. - = unimplemented read as ’0’, q = value depends on condition. Special Function Registers (SFR)
0x stands for hexadecimal