PIC 16x84 Basics

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Special function registers

The special function registers are memory registers which is used for special dedicated functions. These registers perform various dedicated functions inside the PIC chip. Each special function inside this PIC chip is controlled by using these registers. These registers are used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are normally implemented as in the form of static RAM memory. A list of these registers is given in the tables below. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.

SFRs are the gateway to interaction between the CPU and the peripherals. To the CPU, an SFR acts more or less like a normal memory location—you can usually write to it or read from it. What makes it “special” is that the bits of that memory location have a dual purpose. Each bit is wired across to one or other of the microcontroller peripherals. Each is then used either to set up the operating mode of the peripheral or to transfer data between the peripheral and the microcontroller core.

The 16F84 Special File Registers set is organized in two banks, with the most commonly used registers in the default bank 0. Some of the control registers, such as the port data direction registers, TRISA and TRISB, and the OPTION register, are mapped into bank 1. Many of the SFRs can be accessed in either bank. Others have special access instructions, namely TRIS to write the Port A and B data direction registers, and OPTION which is used to set up the real time clock counter.

In another words, SFR is an area of data memory dedicated to registers that are required for configuration and dataflow control. This dedicated memory area is divided into a number of special function registers which can not be used as general purpose registers by the programmer. The special function registers are TMR0, OPTION, PCL, STATUS, FSR, PORTA, PORTB, TRISA, TRISB, EEDATA, EECON1, EEADR, EECON2, PCLATH and INTCON and are situated in the data memory locations shown in Figure below

 

File Address

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit2

Bit 1

Bit 0

Value on

Power-On

 Reset

Value on

Other

 Resets

Bank 0
0x00 INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
0x01 TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
0x02 PCL Least Significant 8 bits of the Program Counter (PC) 0000 0000 0000 0000
b7 b6 b5 b4 b3 b2 b1 b0
0x03 STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
0x04 FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
0x05 PORTA - - -

RA4/

T0CKI

RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu
0x06 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
0x07 Unimplemented Unimplemented location, read as '0 ---- ---- ---- ----
0x08 EEDATA EEPROM data register xxxx xxxx uuuu uuuu
0x09 EEADR EEPROM address register xxxx xxxx uuuu uuuu
0x0A PCLATH - - - Most Significant 5 Bits of the PC ---0 0000 ---0 0000
b12 b11 b10 b9 b8
0x0B INTCON GIE EEIE T0IE INT E RBIE T0IF INTF RBIF 0000 000x 0000 000u
Bank 1
0x80 INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ----
0x81 OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
0x82 PCL Least Significant 8 bits of the Program Counter (PC) 0000 0000 0000 0000
0x83 STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
0x84 FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu
0x85 TRISA - - - PORTA data direction register ---1 1111 ---1 1111
b4 b3 b2 b1 b0
0x86 TRISB PORTB data direction register 1111 1111 1111 1111
b7 b6 b5 b4 b3 b2 b1 b0
0x87 Unimplemented Unimplemented location, read as '0 ---- ---- ---- ----
0x88 EECON1 - - - EEIF WRERR WREN WR RD ---0 x000 ---0 q000
0x89 EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ----
0x8A PCLATH - - - Most Significant 5 Bits of the PC ---0 0000 ---0 0000
b12 b11 b10 b9 b8
0x8b INTCON GIE EEIE T0IE INT E RBIE T0IF INTF RBIF 0000 000x 0000 000u

Legend: x = unknown, u = unchanged. - = unimplemented read as ’0’, q = value depends on condition. Special Function Registers (SFR)

0x stands for hexadecimal