PIC 16x84 Basics
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The INTCON Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF

 

Introduction: The PIC16F84 has four interrupt sources:

  1. Termination of writing data to EEPROM
  2. TMR0 interrupt caused by timer overflow
  3. Interrupt during alteration on RB4, RB5, RB6 and RB7 pins of port B.
  4. External interrupt from RB0/INT pin of microcontroller

Generally speaking, each interrupt source has two bits associated with it. One enables interrupts, and the other detects when interrupts occur. There is one common bit called GIE which can be used to disable or enable all interrupts simultaneously. This bit is very useful when writing a programme because it allows for all interrupts to be disabled for a period of time, so that execution of some important part of a programme would not be interrupted. When the instruction which resets GIE bit is executed (GIE=0, all interrupts disallowed), any interrupt that remained unsolved would be ignored. Interrupts which remained unsolved and were ignored, are processed when GIE bit (GIE=1, all interrupts allowed) would be cleared. When interrupt was answered, GIE bit was cleared so that any additional interrupts would be disabled, return address was pushed onto stack and address 0004h was written in programme counter - only after this does replying to an interrupt begin! After interrupt is processed, the bit which caused an interrupt must be cleared, or the interrupt routine would automatically be processed over again during a return to the main programme.

Interrupt Request Mechanism

 

Interrupt Request Mechanism

 

The INTCON Register:

The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources.

The meaning of INTCON might be (though this is only me thinking) INTurrpt CONtrol register. I have serached the net for the source of this acronym with no avail; if you find it please e-mail me.

Anyway, interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

 

This register is used to configure the interrupt control logic circuitry. Bits 0 to 6 are used to configure the interrupt enable/disable statuses and the interrupt flags for the four interrupt sources. No interrupt to the CPU will result unless the GIE bit is set. The GIE bit is the bit INTCON<7> and when set, enables all un-masked interrupts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

R = Readable bit

W= Writable bit

U = Unimplemented bit, read as ‘0’

-n= Value at POR reset

 

bit 7:

GIE: The Global Interrupt Enable bit is like the master switch for all the different interrupts.
SETTING this bit will enable all the interrupts to function, CLEARING this bit will disable ALL interrupts.
1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6

EEIE: EE Write Complete Interrupt Enable bitEE Write Complete Interrupt Enable bit allows an interrupt to occur when a write operation to the EEPROM has completed. This interrupt may be required in your programs because it takes time for a write operation to EEPROM to complete. This interrupt capability allows the program to do other things instead of halting while the write operation is accomplished. SETTING the EEIE bit allows an interrupt when the write to EEPROM operation is complete; CLEARING the bit disables the interrupt.
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt

 

bit 5

T0IE: The TMR0 Overflow Interrupt Enable bit allows an interrupt when the TMR0 counter overflows from 255 (0xff) to 0 (0x00). Setting this bit allows the TMR0 interrupt, CLEARING this bit will disable the interrupt.
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

 

bit 4:

INTE: The RB0/INT External interrupt Enable bit allows an interrupt from a clocking signal applied to pin RB0. Whether the interrupt occurs on the rising or falling edge of this clocking signal is determined by the state of the INTEDG bit in the OPTION_REG. SETTING the INTE bit allows an interrupt from the signal on RB0, CLEARING this bit disables the interrupt.
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
 

bit 3:

RBIE: The Port Change Interrupt Enable bit allows an interrupt when there is a change of state on pins RB7, RB6, RB5 and RB4 on PORTB. SETTING the RBIE bit will allow the PORTB change interrupts; CLEARING this bit disables the interrupts.
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

 

bit 2:

T0IF: The TMR0 Overflow Interrupt Flag bit is used by the device to indicate if the interrupt was the result of a TMR0 overflow. As you may have noticed, an interrupt code will be triggered by any of the different resources available on the MCU. It is up to you, the programmer, to determine through your software code which of the resources generates the interrupt. Flag bits allow you to make that determination. In this case, when a TMR0 overflow interrupt occurs, the TOIF flag bit is SET. Early in the interrupt service routine (the subroutine program that you will write to deal with an interrupt) , a check of the various flags is accomplished - in this case, the TOIF flag, and if it is SET, a TMR0 interrupt occurred and the program will take the desired action. You reset the TMR0 interrupt by CLEARING the TOIF bit. If you fail to reset the TOIF bit, additional TMR0 interrupts will occur immediately once the interrupt service routine has completed.
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow

 

bit 1:

INTF: The RB0/INT External Interrupt Flag bit is used by the device to indicate if the interrupt was the result of a clocking signal on the RB0 pin. You will need to check the state of INTF in the interrupt service routine to determine if the interrupt occurred because of a clock signal on RB0. At completion of the interrupt service routine, the INTF pin must be CLEARED to prevent unintended interrupts.
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur

 

BIT 0:

RBIF: The Port Change Interrupt Flag bit is used likewise by the device to indicate if the interrupt was the result
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state.

The PIC 16F84’s interrupt logic.

Fig. The PIC 16F84’s interrupt logic.

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